As technology scales, power optimization becomes a significant requirement for the system-on-chip (SoC) designs. Multi-voltage design is an effective approach to optimize power consumption of the SoC, and level shifters (LS) are a key components interfacing the multiple voltage domains. The increased number of multiple voltage domains has increased the use of level-shifters resulting in significant performance and area overheads. However, many of these voltage domains have limited voltage differential (e.g., less than 200 mV), and therefore using conventional large level-shifters can be expensive.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.